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N层的耗尽层分布不同,其决定了击穿电压的极限。 SJ-MOS可以设计为具有较低电阻率的N层,从而实现较低的导通电阻。
SJ-MOS(我们称之为DTMOS)在N层的一部分上形成柱状P层(P-pillar layer),P-N层交替排列。
当应用VDS时,耗尽层会扩展到N层,即漂移层。 然而,普通D-MOS(我们称为 π-MOS)和SJ-MOS的分布不同。(参考电场强度图。电场强度表示耗尽层中的状态。)
在D-MOS中,P/N层之间的界面电场强度最高,当这部分超过材料硅的极限时就会发生击穿现象。这是击穿电压的极限。另外,SJ-MOS在N层中具有均匀的电场强度。
因此,SJ-MOS可以设计为具有较低电阻的N层,从而实现较低的导通电阻。
另请参阅下面的FAQ。