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High-Bandwidth Memory Assembly Technology

Stacked Chip SoC (SCS)

Solder micro-bumps provide high-pin-count chip-to-chip connections, making it possible to realize both high bandwidth and low power consumption.

  • High pin count: 625 bumps/mm2 (40-μm pitch)
  • Low-capacitance wiring: ≤ 0.4 pF (Bonding wire: Approx. 2.5 pF)
  • 1-Gb DRAM x1024, 2-Gb DRAM x2048 2Gb (in mass production)
Chip Structure

Chip Structure

Application Example: Graphics Processor SoC

60% Reduction in Power Consumption Compared to LDDR3
LPDDR3 SCS with Custom DRAM
Total DRAM Power*[W] 3.84 1.50
Data width [bit/unit] 32 2048
# of DRAMs 8 1
interface speed [Mbps] 1600 200
Total bandwidth [GB/s] 50 50

* excluding SoC power



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